GATE || OS || Memory

Let the page fault service time to 10 ms in a computer with average memory access time being 20 ns. If one page fault is generated for every 10⁶ memory accesses, what is the effective access time for the memory?
GATE CSE 2011 - [1Marks] (MCQ)

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a Translation Lookaside Buffer (TLB). Assume that when a page is evicted from main memory, the corresponding blocks in the cache are marked invalid.

For a given memory reference, which of the following sequences of events can NEVER happen? [GATE 2026 || SET-1 MSQ || 2-mark]

[Tex]\begin{aligned} &\text{A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB.} \\ &\text{TLB reach is defined as the total amount of physical memory that} \\ &\text{can be accessed through the TLB entries.} \\ &\text{The paging system uses pages of size 4 KB. The virtual address space is 64 GB} \\ &\text{and physical address space is 1 GB.} \\ &\text{If each TLB entry stores:} \\ &\quad\bullet\ \text{a 4-bit process id} \\ &\quad\bullet\ \text{page number} \\ &\quad\bullet\ \text{frame number} \\ &\quad\bullet\ \text{a 2-bit control field} \\ &\text{then the size of the TLB (in bytes) is \_\_\_\_\_\_.} \\ &\textbf{Note:} \\ &1\text{K} = 2^{10}, 1\text{M} = 2^{20}, 1\text{G} = 2^{30}. \end{aligned}[/Tex]

[GATE 2026 || SET-2 NAT || 2-mark]

Consider contiguous allocation of physical memory to processes using a variable partitioning scheme. Suppose there are 8 holes in the memory of sizes: 20 KB, 4 KB, 25 KB, 18 KB, 7 KB, 9 KB, 15 KB, and 12 KB. Assume that no two holes are adjacent. Two processes arrive in order:

P1 = 16 KB
P2 = 9 KB

They are allocated memory using the best-fit technique. After allocating space to P1 and P2, the number of holes of size less than 8 KB is _______. Note 1K=2¹⁰

[GATE 2026 || SET-2 NAT || 2-mark]

In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows: The OS correctly predicts only up to next 4 page references (including the current page) at the time of allocating a frame to a page. A process accesses the pages in the following order of page numbers: 1, 3, 2, 4, 2, 3, 1, 2, 4, 3, 1, 4. If the system has three memory frames that are initially empty, the number of page faults that will occur during execution of the process is ________ . (Answer in integer)

GATE 2025 CS SET1 - 2Marks (NAT)

A disk of size 512M bytes is divided into blocks of 64K bytes. A file is stored in the disk using linked allocation. In linked allocation, each data block reserves 4 bytes to store the pointer to the next data block. The link part of the last data block contains a NULL pointer (also of 4 bytes). Suppose a file of 1M bytes needs to be stored in the disk. Assume, 1K = 2¹⁰ and 1M = 2²⁰. The amount of space in bytes that will be wasted due to internal fragmentation is ______. (Answer in integer)

GATE 2025 CS1 - 2Marks (NAT)

Consider a demand paging memory management system with 32-bit logical address, 20-bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?
(MCQ-SET-1-2025) - 1Marks

Consider a demand paging system with four-page frames (initially empty) and an LRU page replacement policy. For the following page reference string 7, 2,7,3, 2,5,3, 4,6,7,7,1,5,6,1 the page fault rate, defined as the ratio of number of page faults to the number of memory accesses (rounded off to one decimal place) is_________.
GATE CSE 2022 - [2Marks] (NAT)

Consider four processes P, Q, R, and S scheduled on a CPU as per round-robin algorithm with a time quantum of 4 units. The processes arrive in the order P, Q, R, S, all at time t = 0. There is exactly one context switch from S to Q, exactly one context switch from R to Q, and exactly two context switches from Q to R. There is no context switch from S to P. Switching to a ready process after the termination of another process is also considered a context switch. Which one of the following is NOT possible as CPU burst time (in time units) of these processes?
GATE CSE 2022 - [2Marks] (MCQ)

Consider a computer system with 57-bit virtual addressing using multi-level tree-structured page tables with L levels for virtual to physical address translation. The page size is 4 KB (1 KB = 1024 B) and a page table entry at any of the levels occupies 8 bytes.

The value of L is.........
GATE CSE 2023, Set 2 - 2Marks (NAT)