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GATE || Digital Logic || PYQ || 2026 || Module 5:Sequential Circuits
Question 1
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops [GATE|| 2026 MCQ || Set-1 || 2-mark ]
| Input (P) | Current State | Current State | Next State | Next State |
|---|---|---|---|---|
| Q₁ | Q₀ | Q₁⁺ | Q₀⁺ | |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
[Tex]\begin{aligned} D_1 &= PQ_1 + \bar{P}Q_0 + Q_1Q_0 \\ D_0 &= PQ_0 + \bar{P}Q_1 + Q_1\overline{Q_0} \end{aligned}[/Tex]
[Tex]\begin{aligned} D_1 &= \bar{P}Q_1 + \bar{P}Q_0 + Q_1Q_0 \\ D_0 &= \bar{P}\overline{Q_0} + \bar{P}Q_1 + Q_1\overline{Q_0} \end{aligned}[/Tex]
[Tex]\begin{aligned} D_1 &= \bar{P}\bar{Q}_1 + \bar{P}Q_0 + Q_1Q_0 \\ D_0 &= \bar{P}Q_0 + \bar{P}Q_1 + Q_1\bar{Q}_0 \end{aligned}[/Tex]
[Tex]\begin{aligned} D_1 &= P{Q_1} + \bar{P}Q_0 + Q_1{Q_0} \\ D_0 &= P\overline{Q_0} + \bar{P}Q_1 + Q_1\overline{Q_0} \end{aligned}[/Tex]
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