GATE ||COA || PYQ || 2005-2026 || MACHINE INSTRUCTION & ADRESSING MODE || UPDATED

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Question 1

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y? Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers. [GATE CSE - 2026 MCQ SET – 1 (1-MARKS)]

  • ADD Z, X, Y

  • LOAD R0, X

    ADD Z, R0, Y

  • ADD R0, X, Y

    STORE Z, R0

  • LOAD R0, X

    LOAD R1, Y

    ADD R2, R0, R1

    STORE Z, R2

Question 2

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II.


LIST I

LIST II

P. Immediate

1. Element of an array

Q. Indirect

2. Pointer

R. Base with index

3. Element of a record

S. Base with offset/displacement

4. Constant

[GATE CSE - 2026 MCQ SET – 1 (1-MARKS)]

  • P-4, Q-3, R-1, S-2

  • P-4, Q-2, R-1, S-3

  • P-1, Q-4, R-3, S-2

  • P-2, Q-3, R-1, S-4

Question 3

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions? [GATE CSE - 2026 MCQ SET – 1 (1-MARKS) ]

  • 8

  • 4

  • 64

  • 16

There are 3 questions to complete.

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